1. Field of the Invention
The present invention relates generally to circuit testing and verification. More particularly the present invention relates to a computer implemented method, apparatus and computer program product, in a simulated multiple core integrated circuit, to adjust the time of applying stimuli in the form of first test vector to apply stimuli in the form of a second test vector.
2. Description of the Related Art
As transistor densities in integrated circuits climb, developers have responded by building systems on a chip (SOC). A system on a chip integrates many and sometimes all logical components of a computer within a single integrated circuit. In addition, digital, analog, mixed-signal and radio frequency functions may be placed on a common chip.
As individual chips have become more complex, testing of the SOC has become more challenging. When chip circuit densities were less than half of current circuit densities, a design would be fabricated and attached to a bed-of-nails in order to apply signals directly to the circuits and monitor actual circuit responses. However, such a methodology created unwanted delays in fabricating prototypes, discovering defects and repeating the process on revised prototypes. Consequently, testers of SOCs and other complex integrated circuits moved to an approach of simulating the electrical properties of newly designed circuits.
The design process includes a first step of designing a circuit using Verilog™ or Very High-level Design Language (VHDL). Next designers test circuits at the unit level. Next, the designers test the system as a whole, that is, perform system testing. Verilog™ is a trademark of Cadence, Inc. On one hand, a unit test comprises simulating a component of a SOC. A component can include a microprocessor, bus bridges, direct memory access circuits, and the like. On the other hand, system testing comprises tests on several or all components expected to be placed on a chip or in a package. System testing often includes multiple components communicating over one or more busses. Consequently, some processing occurs in parallel. Thus, test coverage of multiple processes occurring in parallel will potentially reveal defects. Alternatively, broad test coverage may provide some assurance that parallel processing will not cause any errors during production and use of the device under test.
During system testing, test vectors are applied to the SOC so that some operations of each test vector occur concurrently. A tester may trigger test vectors to begin contemporaneously. One vector completes before the second vector. Defects caused by concurrent operation of the vectors will only be apparent for the duration that the vectors are both operating. Unfortunately, there is no testing of the parallel operation of the vectors during the interval after the shorter vector completes. Testers, manufacturers and integrated circuit customers would benefit if shorter test vectors were triggered to begin substantially after the start of a longer test vector.